1. Field
Example embodiments relate to methods of forming a pattern and methods of manufacturing a memory device using the same. Example embodiments relate to methods of forming an active pattern by an epitaxial growth process and methods of manufacturing a memory device using the method of forming the active pattern.
2. Description of the Related Art
Generally, non-volatile memory devices are classified into floating gate type memory devices and/or floating trap type memory devices. A silicon-oxide-nitride-oxide-semiconductor (SONOS) memory device may serve as the floating trap type memory device. The SONOS memory device may include a tunnel insulation layer formed on a semiconductor substrate, a charge trapping layer, a blocking insulation layer and a gate electrode. The tunnel insulation layer may include silicon oxide, the charge trapping layer may include silicon nitride, the blocking insulation layer may include silicon oxide, and the gate electrode may include a conductive material. The SONOS memory device may perform programming tasks by storing electrons in a trap site formed in the charge trapping layer, which is disposed between the gate electrode and the semiconductor substrate, and erasing tasks by storing holes in the trap site formed in the charge trapping layer.
The tunnel insulation layer may be formed to have a relatively small thickness because the electrons and/or the holes may be stored in the trap site of the charge trapping layer. The SONOS memory device may be operated even by a lower operation voltage so that a structure of a peripheral circuit may be simplified. The SONOS memory device may have an increased integration degree.
Recently, a width between isolation regions for isolating memory cells has been decreased as a design rule of the memory cells is reduced. The isolation regions may be formed by forming a photoresist pattern on a substrate, etching the substrate using the photoresist pattern as an etching mask to form a trench at upper portions of the substrate, and filling the trench with an insulator.
Forming the isolation regions using the photoresist pattern may become a challenging task because the design rule of the memory cells has become smaller. As a critical dimension (CD) of the photoresist pattern gets finer, a thickness of the photoresist pattern may get smaller, and thus etching the substrate using the photoresist pattern may result in being more difficult. The photoresist pattern may be fine enough that the photoresist pattern may be broken. Accordingly, a roughness of a side face of the photoresist pattern may not be uniform, thereby disfiguring a shape of the trench that may be successively formed by the etching process.